AT91SAM9G25-CU Datasheet, PDF (474/1102 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

z Incrementing/decrementing or fixed address for source in SRC_INCR field.
z Incrementing/decrementing or fixed address for destination in DST_INCR field.
5. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx regis-
ter for channel x.
6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for
channel x.
7. Write the channel configuration information into the DMAC_CFGx register for channel x.
z i. Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL
bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
z ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign the
handshaking interface to the source and destination peripheral. This requires programming the SRC_PER
and DST_PER bits, respectively.
4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit,
where x is the channel number. Make sure that bit 0 of the DMAC_EN.ENABLE register is enabled.
5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-
memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the
buffer and carries out the buffer transfer.
6. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx register. The DMAC_DADDRx
register remains unchanged. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then sam-
ples the row number as shown in Table 31-3 on page 462. If the DMAC is in Row 1, then the DMAC transfer has
completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. So you
can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or
poll for the enable (ENAx) field in the Channel Status Register (DMAC_CHSR.ENAx bit) until it is cleared by hard-
ware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
7. The DMAC transfer proceeds as follows:
1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel
number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has com-
pleted. It then stalls until STALx bit of DMAC_CHSR is cleared by writing in the KEEPx field of
DMAC_CHER register, where x is the channel number. If the next buffer is to be the last buffer in the DMAC
transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit,
DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in Table 31-3 on page 462. If the next
buffer is not the last buffer in the DMAC transfer, then the automatic transfer mode bit should remain
enabled to keep the DMAC in Row 11 as shown in Table 31-3 on page 462.
2. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = ‘0’, where x is the channel
number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt
Enable register, but starts the next buffer transfer immediately. In this case, the software must clear the
automatic mode bit, DMAC_CTRLBx.AUTO, to put the device into ROW 1 of Table 31-3 on page 462 before
the last buffer of the DMAC transfer has completed.
The transfer is similar to that shown in Figure 31-13 on page 475.
The DMAC Transfer flow is shown in Figure 31-14 on page 476.
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
474