AT91SAM9R64 Datasheet, PDF (90/911 Pages) ATMEL Corporation – Thumb Microcontrollers

When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
Figure 15-6. User Reset State
SLCK
MCK
NRST
proc_nreset
RSTTYP
periph_nreset
Any
Freq.
Resynch.
2 cycles
Any
Resynch.
2 cycles
Processor Startup
= 3 cycles
XXX
0x4 = User Reset
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
15.3.4.4
Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These
commands are performed by writing the Control Register (RSTC_CR) with the following bits at
1:
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory
system, and, in particular, the Remap Command. The Peripheral Reset is generally used for
debug purposes.
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field
ERSTL in the Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these com-
mands can be performed independently or simultaneously. The software reset lasts 3 Slow
Clock cycles.
90 AT91SAM9R64/RL64 Preliminary
6289A–ATARM–15-Jan-08