AT91SAM9R64 Datasheet, PDF (229/911 Pages) ATMEL Corporation – Thumb Microcontrollers

AT91SAM9R64/RL64 Preliminary
24.5.6
Self-refresh Mode
This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register.
In self-refresh mode, the SDRAM device retains data without external clocking and provides its
own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM
device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device
is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh
mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter
or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this
feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR)
and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to
the low-power SDRAM during initialization.
After initialization, as soon as PASR/DS/TCSR fields are modified and self-refresh mode is acti-
vated, the Extended Mode Register is accessed automatically and PASR/DS/TCSR bits are
updated before entry into self-refresh mode.
The SDRAM device must remain in self-refresh mode for a minimum period of t_RAS and may
remain in self-refresh mode for an indefinite period. This is described in Figure 24-6.
Figure 24-6. Self-refresh Mode Behavior
Write
SDRAMC_SRR
SDRAMC_A[12:0]
SRCB = 1
Self Refresh Mode
T_XSR = 3
Row
SDCK
SDCKE
SDCS
RAS
CAS
SDWE
Access Request
to the SDRAM Controller
6289A–ATARM–15-Jan-08
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