AT91SAM9R64 Datasheet, PDF (688/911 Pages) ATMEL Corporation – Thumb Microcontrollers

The host updates the backbuffer while the LCD Controller is displaying the primary buffer. When
the backbuffer has been updated the host updates the DMA Base Address registers.
When using a Dual Panel LCD Module, both base address pointers should be updated in the
same frame. There are two possibilities:
• Check the DMAFRMPTx register to ensure that there is enough time to update the DMA
Base Address registers before the end of frame.
• Update the Frame Base Address Registers when the End Of Frame IRQ is generated.
Once the host has updated the Frame Base Address Registers and the next DMA end of frame
IRQ arrives, the backbuffer and the primary buffer are swapped and the host can work with the
new backbuffer.
When using a dual-panel LCD module, both base address pointers should be updated in the
same frame. In order to achieve this, the DMAUPDT bit in DMACON register must be used to
validate the new base address.
39.9
2D Memory Addressing
The LCDC can be configured to work on a frame buffer larger than the actual screen size. By
changing the values in a few registers, it is easy to move the displayed area along the frame
buffer width and height.
Figure 39-11. Frame Buffer Addressing
Frame Buffer
Base word address &
pixel offset
Displayed Image
Line-to-line
address increment
In order to locate the displayed window within a larger frame buffer, the software must:
• Program the DMABADDR1 (DMABADDR2) register(s) to make them point to the word
containing the first pixel of the area of interest.
• Program the PIXELOFF field of DMA2DCFG register to specify the offset of this first pixel
within the 32-bit memory word that contains it.
• Define the width of the complete frame buffer by programming in the field ADDRINC of
DMA2DCFG register the address increment between the last word of a line and the first word
of the next line (in number of 32-bit words).
• Enable the 2D addressing mode by writing the DMA2DEN bit in DMACON register. If this bit
is not activated, the values in the DMA2DCFG register are not considered and the controller
assumes that the displayed area occupies a continuous portion of the memory.
688 AT91SAM9R64/RL64 Preliminary
6289A–ATARM–15-Jan-08