PS-AT17LV010 Datasheet, PDF (9/15 Pages) ATMEL Corporation – MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 1 MEGABIT SERIAL EEPROM, MONOLITHIC SILICON

PS-AT17LV010
Rev A
CLK to data float
delay when
cascading (2)
CLK to CEO
delay when
cascading (1)
CE to CEO
delay when
cascading (1)
RESET /OE to
CEO delay
when cascading
(1)
T_CDF
T_OCK
T_OCE
T_OOE
3003
3003
3003
3003
V_DD = 3 V &V_DD = 3.6 V, F_MAX
V_DD = 3 V &V_DD = 3.6 V, F_MAX
V_DD = 3 V &V_DD = 3.6 V, F_MAX
V_DD = 3 V &V_DD = 3.6 V, F_MAX
50 ns
4
3
55 ns
3
40 ns
40 ns
3
Notes :
(1)
Output load gate equivalent +C_L <30 pF
(2)
Float delays are measured with 5 pF AC loads. Transition is measured +/- 200 mV from steady-state active levels
(3) Recorded
(4) Go-no-go tested
(5) This parameter is tested initially and after any design or process change which could affect this parameter,
and therefore shall be guaranteed to the limits specified in Table I
(6) All the cases are tested, but only one is recorded (worst case) if required (note 3)
TABLE 2. Parameter drift values
Test
High level output
voltage
Low level output
voltage
Low level Input
current
High level Input
current
Supply current
Standby mode
Sym
bol
V_OH
V_OL
I_IL
I_IH
I_CCS
Test method
Mil-Std-883
As per table 2
As per table 2
As per table 2
As per table 2
As per table 2
Conditions
As per table 2
As per table 2
As per table 2
As per table 2
As per table 2
Drift
limits
0.1
0.1
0.5
0.5
15
Unit
V
V
μA
μA
µA
Note : the above parameter shall be recorded before and after burn-in and life test to determine the delta.
Sheet 9 / 15