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AT17C512A Datasheet, PDF (9/11 Pages) ATMEL Corporation – FPGA Serial Configuration Memories
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AT17C/LV/512A/0
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AC Characteristics for AT17C010A/512A
VCC = 3.3V ± 10% Commercial / VCC = 3.3V ± 10% Ind./Mil
Symbol
TOE(2)
TCE(2)
TCAC(2)
TOH(2)
TDF(3)
TLC
THC
TSCE
THCE
THOE
FMAX(4)
TLC
THC
VRDY
Description
OE to Data Delay
nCS to Data Delay
CLK to Data Delay
Data Hold From nCS, OE, or DCLK
nCS or OE to Data Float Delay
CLK Low Time Slave Mode
CLK High Time Slave Mode
nCS Setup Time to DCLK (to guarantee proper counting)
nCS Hold Time to DCLK (to guarantee proper counting)
OE High Time (Guarantees Counter Is Reset)
MAX Input Clock Frequency Slave Mode
CLK Low Time Master Mode
CLK High Time Master Mode
Ready Pin Open Collector Voltage
Commercial
Min
Max
50
55
60
0
50
25
25
35
0
20
15
30
300
30
300
1.2
2.4
Industrial/Military
Min
Max
55
60
65
0
50
25
25
40
0
20
10
30
300
30
300
1.2
2.4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
V
AC Characteristics for AT17C010A/512A When Cascading
VCC = 3.3V ± 10% Commercial / VCC =3.3V ± 10% Ind./Mil.
Commercial
Industrial/Military
Symbol
Description
Min
Max
Min
Max
Units
TCDF(3)
DCLK to Data Float Delay
50
50
ns
TOCK(2)
DCLK to nCASC Delay
50
55
ns
TOCE(2)
CE to nCASC Delay
35
40
ns
TOOE(2)
OE to nCASC Delay
35
35
ns
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
4. During cascade FMAX = 12.5 MHz
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