AT17C512A Datasheet, PDF (4/11 Pages) ATMEL Corporation – FPGA Serial Configuration Memories

Pin Configurations
Pin Number
(20-Pin PLCC)
2
Pin Name
DATA
4
DCLK
5
WP1
8
RESET/OE
9
nCS
10
GND
12
nCASC
A2
15
READY
18
SER_EN
20
V_CC
Pin Type
Output
I/O
Input
Input
Input
Ground
Output
Input
Output
Input
Power
Description
Serial data output.
Clock output or clock input. Rising edges on DCLK increment the internal address
counter and present the next bit of data to the DATA pin. The counter is incremented
only if the OE input is held high, the nCS input is held low, and all configuration data
has not been transferred to the target device (otherwise, in FPGA 10K master mode,
the DCLK pin drives low).
WRITE PROTECT (1). Used to protect portions of memory during programming. See
programming guide for details.
Output enable (active high) and reset (active low). A low logic level resets the address
counter. A high logic level enables DATA and permits the address counter to count. In
the mode, if this pin is low (reset), the internal oscillator becomes inactive and DCLK
drives low.
Chip select input (active low). A low input allows DCLK to increment the address
counter and enables DATA to drive out. If the AT17A Series is reset with nCS low, the
device initializes as the first device in a daisy-chain. If the AT17A Series is reset with
nCS high, the device initializes as the next AT17A Series device in the chain
A 0.2 µF decoupling capacitor should be placed between the V_CC and GND pins.
Cascade select output (active low). This output goes low when the address counter
has reached its maximum value. In a daisy-chain of AT17A Series devices, the
nCASC pin of one device is usually connected to the nCS input pin of the next device
in the chain, which permits DCLK to clock data from the next AT17A Series device in
the chain.
Device selection input, A2. This is used to enable (or select) the device during
programming, when SER_EN is Low (see Programming Guide for more details)
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. (Recommend a 4.7KΩ Pull-up on this pin if used).
Serial enable is normally high during FPGA loading operations. Bringing SER_EN
Low, enables the two wire serial interface mode for programming.
Power pin.
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .............................-0.1V to V_CC + 0.5V
Supply Voltage (V_CC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 s @ 1/16 in.)..................260°C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
ESD (R_ZAP = 1.5K, C_ZAP = 100 pF) ................................ 2000V
4
AT17C/LV/512A/010A