AT17C512A Datasheet, PDF (3/11 Pages) ATMEL Corporation – FPGA Serial Configuration Memories

AT17C/LV/512A/010A
multi-device configuration. Once the first AT17A Series
device finishes sending configuration data, it drives its
nCASC pin low, which drives the nCS pin of the second
AT17A Series device low. This activates the second AT17A
Series device to send configuration data to the FPGA
device.
The first AT17A Series device clocks all subsequent AT17A
Series devices until configuration is complete. Once all
configuration data is transferred and nCS on the first
AT17A Series device is driven high by CONF_DONE on
the FPGA devices, the first AT17A Series device clocks 16
additional cycles to initialize the FPGA device. Then the
first AT17A Series device goes into zero-power (idle) state.
If nCS on the first AT17A Series device is driven high
before all configuration data is transferred–or if the nCS is
not driven high after all configuration data is transferred–
the nSTATUS is driven low, indicating a configuration error.
Figure 1. FPGA Device Configured with Two AT17A Series Devices
VCC
VCC
1KW
1KW
VCC
Device 1
nCONFIG
DCLK
DATA0
CONF_DONE
MSEL0
nSTATUS
MSEL1
nCE
AT17C010A
Device 1
DCLK
DATA
nCS
nCASC
OE
AT17C010A
Device 2
DCLK
DATA
nCS
OE
GND
GND
3