AT91SAM9R64_14 Datasheet, PDF (888/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

47.2.10 System Controller
47.2.10.1
Possible event loss when reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle the RTT_SR is read, the
corresponding bit might be cleared. This might lead in the loss of this event.
Problem Fix/Workaround
The software must handle RTT event as interrupt and should not poll RTT_SR.
47.2.11 TSADCC
47.2.11.1
TSADCC: Multiple PENCNT detections without NOCNT
In addition to the "Pen Contact" bit (PENCNT), the TSADCC provides a "No Contact" bit
(NOCNT) in its Status Register. When a contact loss is detected by the analog block of the
peripheral, an internal debouncer is started. However, if the contact loss is not validated by the
debouncer (e.g. if it was a glitch), the PENCNT flag is incorrectly set again in the Status Regis-
ter. This results in the PENCNT flag being set multiple times before NOCNT is set.
Problem Fix/Workaround
The user must disregard the value of the PENCNT flag after it has been set once and before the
NOCNT flag has been set. When using interrupts, the interrupt on PENCNT must be disabled
after it has occurred once, and re-enabled when NOCNT occurs.
47.2.12 USART
47.2.12.1
USART: RXBREAK problem when no timeguard
The RXBREAK flag is not correctly handled (FRAME ERROR is set instead) when the time-
guard is 0 and the break character is located just after STOP BIT.
Problem Fix/Workaround
If the NBSTOP = 1, => TIMEGUARD should be different from 0.
SYNCHRONOUS mode is not affected, only ASYNCHRONOUS.
47.2.12.2
USART: DCD is active High instead of Low
DCD signal is active at high level in the USART block (Modem Mode).
DCD should be active at low level.
Problem Fix/Workaround
Add an inverter.
888 AT91SAM9R64/RL64
6289D–ATARM–3-Oct-11