AT91SAM9R64_14 Datasheet, PDF (885/903 Pages) ATMEL Corporation – Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

AT91SAM9R64/RL64
Example with libV3.
• The main code:
//user reset interrupt setting
// Configure AIC controller to handle SSC interrupts
AT91F_AIC_ConfigureIt (
AT91C_BASE_AIC,
// AIC base address
AT91C_ID_SYS,
// System peripheral ID
AT91C_AIC_PRIOR_HIGHEST,
// Max priority
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive
sysc_handler );
// Enable SYSC interrupt in AIC
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
*AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN;
• The C SYS handler:
extern void soft_user_reset(void);
void sysc_handler(void){
//check if interrupt comes from RSTC
if( (*AT91C_RSTC_RSR & AT91C_RSTC_URSTS ) == AT91C_RSTC_URSTS){
soft_user_reset();
//never reached
while(1);
}
}
• The assembler routine:
AREA
TEST, CODE
INCLUDEAT91SAM9xxx.inc
EXPORTsoft_user_reset
soft_user_reset
;disable IRQs
MRS r0, CPSR
ORR r0, r0, #0x80
MSR CPSR_c, r0
;change refresh rate to block all data accesses
LDR r0, =AT91C_SDRAMC_TR
LDR r1, =1
STR r1, [r0]
6289D–ATARM–3-Oct-11
885