AT91SAM9263 Datasheet, PDF (853/1029 Pages) ATMEL Corporation – Thumb Microcontrollers

AT91SAM9263 Preliminary
43.5.2.3
Timegen
The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC,
LCDDEN, used by the LCD module. This block is programmable in order to support different
types of LCD modules and obtain the output clock signals, which are derived from the LCDC
Core clock.
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is
sent through LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can
be selected). The CLKVAL field of LCDCON1 register controls the rate of this signal. The divisor
can also be bypassed with the BYPASS bit in the LCDCON1 register. In this case, the rate of
LCDDOTCK is equal to the frequency of the LCDC Core clock. The minimum period of the LCD-
DOTCK signal depends on the configuration. This information can be found in Table 43-11.
f_LCDDOTCK
=
---^f--^L---^C---^D----^C---^_---^c--^l-^o---^c--^k----
2 × CLKVAL
The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the
LCDCON2 register:
• Always Active (used with TFT LCD Modules)
• Active only when data is available (used with STN LCD Modules)
Table 43-11. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
Configuration
DISTYPE
SCAN
IFWIDTH
LCDDOTCK Period
TFT
1
STN Mono
Single
4
4
STN Mono
Single
8
8
STN Mono
Dual
8
8
STN Mono
Dual
16
16
STN Color
Single
4
2
STN Color
Single
8
2
STN Color
Dual
8
4
STN Color
Dual
16
6
The LCDDEN signal indicates valid data in the LCD Interface.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to
cause the line to be displayed on the panel.
The following timing parameters can be configured:
• Vertical to Horizontal Delay (VHDLY): The delay between begin_of_line and the generation of
LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to
(VHDLY+1) LCDDOTCK cycles.
6249B–ATARM–14-Dec-06
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