AT91SAM9263 Datasheet, PDF (448/1029 Pages) ATMEL Corporation – Thumb Microcontrollers

31.6 Functional Description
31.6.1
Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.
The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO
line is wired on the receiver input and the MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the
transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for
other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate
generator is activated only in Master Mode.
31.6.2
Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is
programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed
with the NCPHA bit. These two parameters determine the edges of the clock signal on which
data is driven and sampled. Each of the two parameters has two possible states, resulting in
four possible combinations that are incompatible with one another. Thus, a master/slave pair
must use the same parameter pair values to communicate. If multiple slaves are used and
fixed in different configurations, the master must reconfigure itself each time it needs to com-
municate with a different slave.
Table 31-2 shows the four modes and corresponding parameter settings.
Table 31-2.
SPI Bus Protocol Mode
SPI Mode
0
1
2
3
CPOL
0
0
1
1
NCPHA
1
0
1
0
Figure 31-3 and Figure 31-4 show examples of data transfers.
448 AT91SAM9263 Preliminary
6249B–ATARM–14-Dec-06