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SAM3U_14 Datasheet, PDF (828/1187 Pages) ATMEL Corporation – From 64 to 256 Kbytes embedded Flash | |||
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a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
reading the DMAC_EBCISR register.
c. Program a List of descriptors.
d. The LLI(n).DMAC_SADDRx memory location for channel x must be set to the loca-
tion of the source data. When the first data location is not word aligned, the two
LSB bits define the temporary value called dma_offset. The two LSB bits of
LLI(n).DMAC_SADDRx must be set to 0.
e. The LLI(n).DMAC_DADDRx register for channel x must be set with the starting
address of the HSMCI_FIFO address.
f. Program LLI(n).DMAC_CTRLAx register of channel x with the following fieldâs
values:
âDST_WIDTH is set to WORD.
âSRC_WIDTH is set to WORD.
âDCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
âBTSIZE is programmed with CEILING((block_length + dma_offset)/4).
g. Program LLI(n).DMAC_CTRLBx register for channel x with the following fieldâs
values:
âDST_INCR is set to INCR.
âSRC_INCR is set to INCR.
âDST_DSCR is set to 0 (fetch operation is enabled for the destination).
âSRC_DSCR is set to 1 (source address is contiguous).
âFC field is programmed with memory to peripheral flow control mode.
âBoth DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
âDIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA
Controller is able to prefetch data and write HSMCI simultaneously.
h. Program LLI(n).DMAC_CFGx register for channel x with the following fieldâs values:
âFIFOCFG defines the watermark of the DMA channel FIFO.
âDST_H2SEL is set to true to enable hardware handshaking on the destination.
âSRC_REP is set to 0. (contiguous memory access at block boundary)
âDST_PER is programmed with the hardware handshaking ID of the targeted
HSMCI Host Controller.
i. If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the
start address of LLI(n+1).
j. Program DMAC_CTRLBx for channel register x with 0. Its content is updated with
the LLI fetch operation.
k. Program DMAC_DSCRx for channel register x with the address of the first descrip-
tor LLI(0).
l. Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting
for request.
7. Poll CBTC[x] bit in the DMAC_EBCISR Register.
8. If a new list of buffers shall be transferred, repeat step 6. Check and handle HSMCI
errors.
9. Poll FIFOEMPTY field in the HSMCI_SR.
828 SAM3U Series
6430FâATARMâ21-Feb-12
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