SAM3U_14 Datasheet, PDF (69/1187 Pages) ATMEL Corporation – From 64 to 256 Kbytes embedded Flash

SAM3U Series
13.4.1.1 Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
13.4.1.2 Device
The processor preserves transaction order relative to other transactions to Device or Strongly-
ordered memory.
13.4.1.3
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
The additional memory attributes include.
13.4.1.4
Shareable
For a shareable memory region, the memory system provides data synchronization between
bus masters in a system with multiple bus masters, for example, a processor with a DMA
controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, software must ensure data
coherency between the bus masters.
13.4.1.5
Execute Never (XN)
Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an
XN region causes a memory management fault exception.
13.4.2
Memory system ordering of memory accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing this does not affect the behavior of the instruction sequence. Nor-
mally, if correct program execution depends on two memory accesses completing in program
order, software must insert a memory barrier instruction between the memory access instruc-
tions, see “Software ordering of memory accesses” on page 71.
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before
A2 in program order, the ordering of the memory accesses caused by two instructions is:
A2
A1
Normal access
Device access, non-shareable
Device access, shareable
Strongly-ordered access
Normal
access
-
-
-
-
Device access
Non-shareable Shareable
-
-
<
-
-
<
<
<
Strongly-
ordered
access
-
<
<
<
Where:
- Means that the memory system does not guarantee the ordering of the accesses.
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6430F–ATARM–21-Feb-12