ATR2731 Datasheet, PDF (8/26 Pages) ATMEL Corporation – DAB One-chip Front End

5. IF Part
5.1 IF Gain-controlled Amplifier
The signal applied to the balanced input pins IFIN1 and IFIN2 is amplified by a gain-controlled IF
amplifier. The gain-control signal is generated by an IF AGC voltage-generation block which is
described in the next section. To avoid offset problems, the output of the gain-controlled ampli-
fier is fed to an amplifier/mixer combination by AC coupling.
5.2 IF Gain-controlled Amplifier/Mixer Combination
Depending on the setting of the two-wire bus bits M2, M3, the output signal of the gain-controlled
IF amplifier is either mixed down to a lower, second IF or, after passing an output buffer stage,
amplified before it appears at the single-ended output pin IFOUT. If the down-conversion option
is chosen, this circuit still offers two possibilities concerning the synthesis of the IF mixer’s LO
signal. This LO signal is derived from the PLL's on-chip reference oscillator. By means of the
two-wire bus bits M2 and M3, it can be decided whether the reference frequency is doubled
before it is given to the mixer's LO port, or if it is used directly. The gain-control voltage of the
amplifier/mixer combination is similar to the gain-controlled IF amplifier generated by an internal
gain-control circuit.
5.3 IF AGC Voltage-generation Block
The purpose of this gain-control circuit in the IF part is to measure the power of the incoming sig-
nal at the balanced input pins IFAGCIN1 and IFAGCIN2, to compare it with a certain power
level, and to generate a control voltage for the IF gain-controlled amplifiers and mixer. This
architecture offers the possibility of ensuring an optimal use of the dynamic range of the A/D
converter which transforms the output signal at pin IFOUT from the analog to the digital domain
despite possible insertion losses of (anti-aliasing) filters which are arranged in front of the con-
verter. Such a constellation is indicated in the application circuit in Figure 12-1 on page 20.
The incoming signal at the balanced input pins IFAGC1 and IFAGC2 passes a power-measure-
ment process similar to that described in “RF AGC Voltage-generation Block” on page 7. For
flexibility reasons, no band-pass filtering is implemented. The voltage derived in this process is
compared to a voltage threshold (th3) which is defined by an on-chip 4-bit D/A converter. The
setting of this converter is defined by the two-wire bus bits TCi (i = 1, 2, 3, 4). Depending on the
result of this comparison, a charge pump feeds a positive or negative current to pin CPIF in
order to charge or discharge an external capacitor. The current of this charge pump can be
selected using the pins WAGC and SLI (Table 5-1):
Table 5-1. Current of Charge Pump
WAGC
SLI
High
X
Low
Low
Low
High
The function can be seen in Figure 13-6 on page 24.
Charge-pump Current
Off
50 µA (slow mode)
190 µA (fast mode)
8 ATR2731
4904A–DAB–03/06