ATR2731 Datasheet, PDF (10/26 Pages) ATMEL Corporation – DAB One-chip Front End

6.2 Reference Divider
Starting from a minimum value, the scaling factor SF_ref of the 9-bit reference divider is freely pro-
grammable by means of the two-wire bus bits r_i (i = 0, ..., 8) according to
∑ ^SFref ^{= r}i ^{× 2i}
If, for example, a frequency raster of 16 kHz is requested, the scaling factor of the reference
divider has to be specified in such a way that the division process results in an output frequency
which is four times higher than the desired frequency raster; that is, the comparison frequency of
the phase detector equals four times the frequency raster. By changing the division ratio of the
main divider from N to N+1 in an appropriate way (fractional-N technique), this frequency raster
is interpolated to deliver a frequency spacing of 16 kHz. So, effectively, a reference scaling
divide factor
∑ ^SFref,eff ^{= 4 × r}i ^{× 2i}
is achieved.
By setting the two-wire bus bit T, a test signal representing the divided input signal can be moni-
tored at the switching output SWA.
7. Main Divider
The main divider consists of a fully programmable 13-bit divider which defines a division ratio N.
The applied division ratio is either N or N + 1 according to the control of a special control unit. On
average, the scaling factors SF = N + k / 4 can be selected where k = 0, 1, 2 or 3.
In this way, VCO frequencies f_VCO = 4 × (N + k / 4) × f_ref / (4 × SF_ref) can be synthesized starting
from a reference frequency f_ref. If we define SF_eff = 4 × N + k and SF_ref,eff = 4 × SF_ref (from the
previous section), then f_VCO = SF_eff × f_ref / SF_ref,eff, where SF_eff is defined by 15 bits.
In the following, this circuit is described in terms of SF_eff and SF_ref,eff. SF_eff has to be pro-
grammed via the two-wire bus interface. An effective scaling factor from 2048 to 32767 can be
selected by means of the two-wire bus bits n_i (i = 0, ..., 14) according to
∑ ^SFeff ^{= n}i ^{× 2i}
By setting the two-wire bus bit T, a test signal representing the divided input signal can be moni-
tored at the switching output SWC.
When the supply voltage is switched on, both the reference divider and the programmable
divider are kept in RESET state until a complete scaling factor is written onto the chip. Changes
in the setting of the programmable divider become active when the corresponding two-wire bus
transmission is completed. An internal synchronization procedure ensures that such changes do
not become active while the charge pump is sourcing or sinking current at its output pin. This
behavior allows a smooth tuning of the output frequency without restricting the controlled VCO's
frequency spectrum.
10 ATR2731
4904A–DAB–03/06