AT17LV010-10DP_05 Datasheet, PDF (8/11 Pages) ATMEL Corporation – Space FPGA Configuration EEPROM

AC Characteristics
V_CC = 3.3V ± 0.3V
Military
Symbol
T_OE(1)
T_CE(1)
T_CAC(1)
T_OH
T_DF(2)
T_LC
T_HC
T_SCE
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK
(to guarantee proper counting)
Min
Max
55
60
60
0
50
25
25
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
T_HCE
CE Hold Time from CLK
(to guarantee proper counting)
0
ns
T_HOE
F_MAX
OE High Time (guarantees counter is reset)
Maximum Clock Frequency
25
10
ns
MHz
Notes: 1. AC test lead = 60 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV
from steady-state active levels.
AC Characteristics when
Cascading
V_CC = 3.3V ± 0.3V
Military
Symbol
Description
Min
Max
Units
T_CDF(2)
T_OCK(1)
T_OCE(1)
T_OOE(1)
F_MAX
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Clock Frequency
50
ns
55
ns
40
ns
40
ns
10
MHz
Notes: 1. AC test lead = 60 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV
from steady-state active levels.
8 AT17LV010-10DP
4265C–AERO–05/05