AT17LV010-10DP_05 Datasheet, PDF (5/11 Pages) ATMEL Corporation – Space FPGA Configuration EEPROM

AT17LV010-10DP
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17LV
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the Atmel AT40KEL applications.
Control of
Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are sim-
ple and self-explanatory.
• The DATA output of the AT17LV010-10DP configurator drives DIN of the FPGA
devices.
• The master FPGA CCLK output drives the CLK input of the AT17LV010-10DP
configurator.
• The CEO output of any AT17LV010-10DP configurator drives the CE input of the
next configurator in a cascaded chain of EEPROMs.
• SER_EN must be connected to V_CC (except during ISP).
• The READY pin is available as an open-collector indicator of the device’s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator
asserts its CEO output Low and disables its DATA line driver. The second configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
AT17LV010-10DP
Reset Polarity
The AT17LV010-10DP configurator allows the user to program the reset polarity as
either RESET/OE or RESET/OE. This feature is supported by industry-standard pro-
grammer algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at V_CC supply
only. Programming super voltages are generated inside the chip. For more information
see application note:
http://www.atmel.com/dyn/resources/prod_documents/doc0437.pdf
Standby Mode
The AT17LV010-10DP configurator enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17LV010-10DP configurator consumes less than
100 µA of current at 3.3V. The output remains in a high-impedance state regardless of
the state of the OE input.
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