ATMEGA329V_0611 Datasheet, PDF (77/375 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

ATmega329/3210/649/6410
Table 41. Overriding Signals for Alternate Functions in PE3:PE0
Signal
Name
PE3/AIN1/
PCINT3
PE2/XCK/AIN0/ PE1/TXD/
PCINT2
PCINT1
PE0/RXD/PCINT
0
PUOE
0
XCK OUTPUT
ENABLE
TXEN
RXEN
PUOV
0
XCK
0
PORTE0 • PUD
DDOE
0
0
TXEN
RXEN
DDOV
0
0
1
0
PVOE
0
0
TXEN
0
PVOV
0
0
TXD
0
PTOE
–
–
–
–
DIEOE
(PCINT3 •
PCIE0) +
AIN1D⁽¹⁾
(PCINT2 •
PCIE0) +
AIN0D⁽¹⁾
PCINT1 • PCIE0 PCINT0 • PCIE0
DIEOV
PCINT3 • PCIE0 PCINT2 • PCIE0 1
1
DI
PCINT3 INPUT XCK/PCINT2
PCINT1 INPUT RXD/PCINT0
INPUT
INPUT
AIO
AIN1 INPUT
AIN0 INPUT
–
–
Note: 1. AIN0D and AIN1D is described in “DIDR1 – Digital Input Disable Register 1” on page
202.
Alternate Functions of Port F
The Port F has an alternate function as analog input for the ADC as shown in Table 42.
If some Port F pins are configured as outputs, it is essential that these do not switch
when a conversion is in progress. This might corrupt the result of the conversion. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and
PF4(TCK) will be activated even if a reset occurs.
Table 42. Port F Pins Alternate Functions
Port Pin Alternate Function
PF7
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
PF6
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
PF5
ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
PF4
ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)
PF3
ADC3 (ADC input channel 3)
PF2
ADC2 (ADC input channel 2)
PF1
ADC1 (ADC input channel 1)
PF0
ADC0 (ADC input channel 0)
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin.
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