ATMEGA329V_0611 Datasheet, PDF (133/375 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

ATmega329/3290/649/6490
8-bit Timer/Counter2
with PWM and
Asynchronous
Operation
Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.
The main features are:
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)
• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 54. For the
actual placement of I/O pins, refer to “Pinout ATmega3290/6490” on page 2. CPU
accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-
specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register
Description” on page 144.
Figure 54. 8-bit Timer/Counter Block Diagram
TCCRnx
count
clear
direction
Control Logic
BOTTOM
TOP
Timer/Counter
TCNTn
= 0 = 0xFF
=
clk_Tn
Prescaler
OCnx
(Int.Req.)
Waveform
Generation
TOVn
(Int.Req.)
T/C
Oscillator
TOSC1
TOSC2
clk_I/O
OCnx
OCRnx
Registers
2552H–AVR–11/06
Status flags
Synchronized Status flags
Synchronization Unit
ASSRn
asynchronous mode
select (ASn)
clk_I/O
clk_ASY
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers.
Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag
Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask
Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously
clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous
operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select
logic block controls which clock source the Timer/Counter uses to increment (or decre-
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