ATMEGA329V_0611 Datasheet, PDF (248/375 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

Scanning the RESET Pin
Figure 111. General Port Pin Schematic Diagram
See Boundary-scan
Description for Details!
PUExn
OCxn
QD
DDxn
Q CLR
RESET
PUD
WDx
RDx
Pxn
IDxn
ODxn
SLEEP
1
QD
PORTxn
0
Q CLR
RESET
RRx
SYNCHRONIZER
DQ
LQ
DQ
PINxn
Q
RPx
CLK _I/O
WPx
WRx
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
CLK I/O :
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
I/O CLOCK
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active
high logic for High Voltage Parallel programming. An observe-only cell as shown in Fig-
ure 112 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal;
RSTHV.
Figure 112. Observe-only Cell
ShiftDR
To
Next
Cell
From System Pin
0
1
FF1
DQ
To System Logic
From
Previous
Cell
ClockDR
248 ATmega329/3290/649/6490
2552H–AVR–11/06