ATA6617C_14 Datasheet, PDF (74/274 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

4.7.3.3 Watchdog Timer Control Register - WDTCR
Bit
Read/Write
Initial Value
7
WDIF
R/W
0
6
WDIE
R/W
0
5
WDP3
R/W
0
4
WDCE
R/W
0
3
WDE
R/W
X
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
WDTCR
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the watchdog timer and the watchdog timer is configured for interrupt. WDIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a
logic one to the flag. When the I-bit in SREG and WDIE are set, the watchdog time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the status register is set, the Watchdog Interrupt is enabled. If WDE is cleared
in combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if time-
out in the watchdog timer occurs.
If WDE is set, the watchdog timer is in interrupt and system reset mode. The first time-out in the watchdog timer will set
WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the watchdog
goes to system reset mode). This is useful for keeping the watchdog timer security while using the interrupt. To stay in
interrupt and system reset mode, WDIE must be set after each interrupt. This should however not be done within the
interrupt service routine itself, as this might compromise the safety-function of the watchdog system reset mode. If the
interrupt is not executed before the next time-out, a system reset will be applied.
If the watchdog timer is used as clock monitor (c.f. Section • “Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0” on page 60), the
system reset mode is enabled and the interrupt mode is automatically disabled.
Table 4-18. Watchdog Timer Configuration
Clock
Monitor
WDTON WDE WDIE Mode
Action on Time-out
x
0
0
0 Stopped
None
On
y⁽¹⁾
y⁽¹⁾
y⁽¹⁾ System reset mode
Reset
0
0
1 Interrupt mode
Interrupt
0
1
0 System reset mode
Reset
Off
0
1
1
Interrupt and system reset mode
Interrupt, then go to system reset
mode
1
x
x System reset mode
Reset
Note: 1. At least one of these three enables (WDTON, WDE and WDIE) equal to 1
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler
bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF
must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the
failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling
values and their corresponding time-out periods are shown in Table 4-19 on page 75.
74 ATA6616C/ATA6617C [DATASHEET]
9132I–AUTO–06/14