ATA6617C_14 Datasheet, PDF (109/274 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

4.11.7.4Phase Correct PWM Mode
The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option.
The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX
and then from MAX to BOTTOM. In non-inverting compare output mode, the output compare (OC0A) is cleared on the
compare match between TCNT0 and OCR0A while upcounting, and set on the compare match while downcounting. In
inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is
incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The
TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 4-36. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent
compare matches between OCR0A and TCNT0.
Figure 4-36. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt
Flag Set
OCRnx Update
TOVn Interrupt
Flag Set
TCNTn
OCnx
(COMnx[1:0] = 2)
OCnx
Period
(COMnx[1:0] = 3)
1
2
3
The Timer/Counter overflow flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to
generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the
COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM0A1:0 to three (See Table 4-32 on page 114). The actual OC0A value will only be visible on the port pin if the data
direction for the port pin is set as output.
The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and
TCNT0 when the counter increments, and setting (or clearing) the OC0A register at compare match between OCR0A and
TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated
by the following equation:
f_OCnxPCPWM = _N--f--^c--_×^l--^k--^_-5-^I--^/_1-^O--0--
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase
correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the
output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
ATA6616C/ATA6617C [DATASHEET] 109
9132I–AUTO–06/14