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| ATA6617C_14 Datasheet, PDF (264/274 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog | |||
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4.27 Instruction Set Summary (Continued)
Mnemonics Operands
Description
BRNE
k
Branch if not equal
BRCS
k
Branch if carry set
BRCC
k
Branch if carry cleared
BRSH
k
Branch if same or higher
BRLO
k
Branch if lower
BRMI
k
Branch if minus
BRPL
k
Branch if plus
BRGE
k
Branch if greater or equal, signed
BRLT
k
Branch if less than zero, signed
BRHS
k
Branch if half carry flag set
BRHC
k
Branch if half carry flag cleared
BRTS
k
Branch if T flag set
BRTC
k
Branch if T flag cleared
BRVS
k
Branch if overflow flag is set
BRVC
k
Branch if overflow flag is cleared
BRIE
k
Branch if interrupt enabled
BRID
k
Branch if interrupt disabled
Bit and Bit-test Instructions
SBI
P,b
Set Bit in I/O register
CBI
P,b
Clear Bit in I/O register
LSL
Rd
Logical shift left
LSR
Rd
Logical shift right
ROL
Rd
Rotate left through carry
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Rotate right through carry
Arithmetic shift right
Swap nibbles
Flag set
Flag clear
Bit store from register to T
Bit load from T to register
Set carry
Clear carry
Set negative flag
Clear negative flag
Set zero flag
Clear zero flag
Global interrupt enable
Global interrupt disable
Set signed test flag
Clear signed test flag
Set twos complement overflow.
Clear twos complement overflow
Set T in SREG
264 ATA6616C/ATA6617C [DATASHEET]
9132IâAUTOâ06/14
Operation
if (Z = 0) then PC â PC + k + 1
if (C = 1) then PC â PC + k + 1
if (C = 0) then PC â PC + k + 1
if (C = 0) then PC â PC + k + 1
if (C = 1) then PC â PC + k + 1
if (N = 1) then PC â PC + k + 1
if (N = 0) then PC â PC + k + 1
if (N â V= 0) then PC â PC + k + 1
if (N â V= 1) then PC â PC + k + 1
if (H = 1) then PC â PC + k + 1
if (H = 0) then PC â PC + k + 1
if (T = 1) then PC â PC + k + 1
if (T = 0) then PC â PC + k + 1
if (V = 1) then PC â PC + k + 1
if (V = 0) then PC â PC + k + 1
if (I = 1) then PC â PC + k + 1
if (I = 0) then PC â PC + k + 1
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clocks
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
I/O(P,b) â 1
None
2
I/O(P,b) â 0
None
2
Rd(n+1) â Rd(n), Rd(0) â 0
Z,C,N,V
1
Rd(n) â Rd(n+1), Rd(7) â 0
Z,C,N,V
1
Rd(0) â C,Rd(n+1) â Rd(n),C
â Rd(7)
Z,C,N,V
1
Rd(7) âC,Rd(n) â Rd(n+1),C
â Rd(0)
Z,C,N,V
1
Rd(n) â Rd(n+1), n=0..6
Z,C,N,V
1
Rd(3..0) â Rd(7..4),Rd(7..4)
â Rd(3..0)
None
1
SREG(s) â 1
SREG(s)
1
SREG(s) â 0
SREG(s)
1
T â Rr(b)
T
1
Rd(b) â T
None
1
Câ1
C
1
Câ0
C
1
Nâ1
N
1
Nâ0
N
1
Zâ1
Z
1
Zâ0
Z
1
Iâ1
I
1
Iâ0
I
1
Sâ1
S
1
Sâ0
S
1
Vâ1
V
1
Vâ0
V
1
Tâ1
T
1
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