AT24C01ASC_14 Datasheet, PDF (7/14 Pages) ATMEL Corporation – Schmitt Trigger, Filtered Inputs for Noise Suppression

AT24C01ASC/02SC/04SC/08SC/16SC
Device Addressing
The 1K, 2K, 4K, 8K, and 16K EEPROM devices all require an 8-bit device address word
following a start condition to enable the chip for a read or write operation (see Figure 6
on page 7).
The device address word consists of a mandatory “1”, “0”, “1”, “0” sequence for the first
four most significant bits as shown. This is common to all the serial EEPROM devices.
The next three bits of the device address word are the most significant data word
address bits for the AT24C16SC (16K), which requires a total of 11 address bits. The
AT24C08SC (8K) requires only 10 total word address bits. The most significant two bits
are included in the device address word. The unused bit of the device address word
should be set to “0”. The AT24C04SC (4K) requires only nine total data word address
bits. The most significant bit is included in the device address word. The two unused bits
of the device address word should be set to “0”. The AT24C02SC (2K) and
AT24C01ASC (1K) do not require any address bits in the device address word. The
three unused bits of the device address word should be set to “0”.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0” (ACK). If a suc-
cessful compare is not made, the chip will return to a standby state (NO ACK).
Figure 6. Device Address
1K/2K ^{1 0 1 0 0 0 0 R/W}
MSD
LSB
4K ^{1 0 1 0 0 0 P0 R/W}
8K ^{1 0 1 0 0 P1 P0 R/W}
16K ^{1 0 1 0 P2 P1 P0 R/W}
Note: P0, P1, P2 = Data word address bits
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1610B–SEEPR–04/04