AT24C01ASC_14 Datasheet, PDF (4/14 Pages) ATMEL Corporation – Schmitt Trigger, Filtered Inputs for Noise Suppression

Table 4. AC Characteristics⁽¹⁾ (Continued)
Symbol
Parameter
Min
Max
Units
t_HD.STA
Start Hold Time
0.6
µs
t_SU.STA
Start Setup Time
0.6
µs
t_HD.DAT
Data In Hold Time
0
µs
t_SU.DAT
t_R
t_F
Data In Setup Time
Inputs Rise Time⁽²⁾
Inputs Fall Time⁽²⁾
100
ns
0.3
µs
300
ns
t_SU.STO
Stop Setup Time
0.6
µs
t_DH
Data Out Hold Time
50
ns
t_WR
Endurance⁽¹⁾
Write Cycle Time
5.0V, 25°C, Byte Mode
5
ms
1M
Write Cycles
Note: 1. Applicable over recommended operating range from T_A = 0°C to +70°C, V_CC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF
(unless otherwise noted)
2. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL-low time periods (see
Figure 3 on page 5). Data changes during SCL-high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
that must precede any other command (see Figure 4 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the Stop command will place the EEPROM in a standby power
mode (see Figure 4 on page 6).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. Each word requires the receiver to acknowledge that it has
received a valid command or data byte. During the transmission of commands from the
host to the EEPROM, the EEPROM will send a zero to the host to acknowledge that it
has received a valid command byte. This occurs on the ninth clock cycle of the com-
mand byte. During read operations, the host will send a zero to the EEPROM to
acknowledge that it has received a valid data byte and that it requests the next sequen-
tial data byte to be transmitted during the subsequent eight clock cycles. This occurs on
the ninth clock cycle of the data byte. If the host does not transmit this acknowledge bit,
the EEPROM will disable the read operation and return to standby mode.
STANDBY MODE: The AT24C01ASC/02SC/04SC/08SC/16SC feature a low-power
standby mode that is enabled upon power-up and after the receipt of the stop bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss, or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
4 AT24C01ASC/02SC/04SC/08SC/16SC
1610B–SEEPR–04/04