AT24C01ASC_14 Datasheet, PDF (5/14 Pages) ATMEL Corporation – Schmitt Trigger, Filtered Inputs for Noise Suppression

Timing Diagrams
Bus Timing
AT24C01ASC/02SC/04SC/08SC/16SC
Figure 1. Bus Timing
Write Cycle Timing
Note: SCL: Serial Clock, SDA: Serial Data I/O
Figure 2. Write Cycle Timing
Data Validity
t_WR(1)
Notes: 1. The write cycle time t_WR is the time from a valid stop condition of a write sequence to
the end of the internal clear/write cycle.
2. SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
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1610B–SEEPR–04/04