AT91SAM9G35-CU Datasheet, PDF (608/1224 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

34.13 Write Protection Registers
To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address
offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register”
(HSMCI_WPMR).
If a write access to anywhere in the HSMCI address space from address offset 0x000 to 0x00FC is detected, then the
WPVS flag in the HSMCI Write Protect Status Register (HSMCI_WPSR) is set and the field WPVSRC indicates in which
register the write access has been attempted.
The WPVS flag is reset by writing the HSMCI Write Protect Mode Register (HSMCI_WPMR) with the appropriate access
key, WPKEY.
The protected registers are:
z “HSMCI Mode Register” on page 611
z “HSMCI Data Timeout Register” on page 612
z “HSMCI SDCard/SDIO Register” on page 613
z “HSMCI Completion Signal Timeout Register” on page 618
z “HSMCI DMA Configuration Register” on page 630
z “HSMCI Configuration Register” on page 631
SAM9G35 [DATASHEET]
11053D–ATARM–11-Feb-13
608