AT91SAM9G35-CU Datasheet, PDF (214/1224 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

23.5.4 Output Control
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O
line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and
PIO_ABCDSR2 (ABCD Select Registers) determines whether the pin is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing
PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are
detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an
input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR
(Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status
Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR
whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables
configuration of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven
on the I/O line.
23.5.5 Synchronous Data Output
Clearing one (or more) PIO line(s) and setting another one (or more) PIO line(s) synchronously cannot be done by using
PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different registers. To
overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output
Data Status Register).Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in
PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR
(Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
23.5.6 Multi Drive Control (Open Drain)
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several
drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling
of the internal one) is generally required to guarantee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable
Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a
peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external
drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
23.5.7 Output Line Timings
Figure 23-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing
PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 23-4 also shows when the
feedback in PIO_PDSR is available.
SAM9G35 [DATASHEET]
11053D–ATARM–11-Feb-13
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