AT91SAM9G35-CU Datasheet, PDF (1181/1224 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

Table 46-23. In Full Speed
Symbol
Parameter
t_FR
t_FE
t_FRFM
Transition Rise Time
Transition Fall Time
Rise/Fall time Matching
Conditions
C_LOAD = 50 pF
C_LOAD = 50 pF
Min
Typ
Max
Unit
4
20
ns
4
20
ns
90
111.11
%
46.13 Analog-to-Digital Converter (ADC)
Table 46-24. Channel Conversion Time and ADC Clock
Parameter
Conditions
ADC Clock Frequency
10-bit resolution mode
Startup Time
Return from Idle Mode
Track and Hold Acquisition Time (TTH)
Conversion Time (TCT)
Throughput Rate
ADC Clock = 13.2 MHz⁽¹⁾
ADC Clock = 13.2 MHz⁽¹⁾
ADC Clock = 5 MHz⁽¹⁾
ADC Clock = 13.2 MHz⁽¹⁾
ADC Clock = 5 MHz⁽¹⁾
Note: 1. The Track-and-Hold Acquisition Time is given by:
Min
Typ
Max
Units
13.2
MHz
40
μs
0.5
μs
1.74
µs
4.6
440
kSPS
192
TTH (ns) = 500 + (0.12 × Z_IN)(Ω)
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conver-
sion time is given by:
TCT(μs) = ---²---³----(MHz)
Fclk
The full speed is obtained for an input source impedance of < 50 Ω maximum, or TTH = 500 ns.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according
to this Track and Hold Acquisition Time, also called Sampled and Hold Time.
Table 46-25. External Voltage Reference Input
Parameter
Conditions
Min
Typ
Max
Units
ADVREF Input Voltage Range
2.4
VDDANA
V
ADVREF Average Current
600
µA
Current Consumption on VDDANA
600
µA
Table 46-26. Analog Inputs
Parameter
Input Voltage Range
Input Peak Current
Input Capacitance
Input Impedance
Min
Typ
Max
Units
0
ADVRE
F
V
2.5
mA
7
10
pF
50
Ω
SAM9G35 [DATASHEET] 1181
11053D–ATARM–11-Feb-13