AT91SAM9G35-CU Datasheet, PDF (446/1224 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

30.7.10 DDRSDRC High Speed Register
Name:
DDRSDRC_HS
Address: 0xFFFFE82C
Access:
Read-write
Reset:
See Table 30-16
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
DIS_ANTICIP_RE
AD
–
–
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 447.
• DIS_ANTICIP_READ: Anticip Read Access
0 = anticip read access is enabled.
1 = anticip read access is disabled (default).
DIS_ANTICIP_READ allows DDR2 read access optimization with multi-port.
As this feature is based on the “bank open policy”, the software must map different buffers in different DDR2 banks to take advan-
tage of that feature.
SAM9G35 [DATASHEET]
11053D–ATARM–11-Feb-13
446