AT83SND2C_14 Datasheet, PDF (60/242 Pages) ATMEL Corporation – MPEG I/II-Layer 3 Hardwired Decoder

12. Watchdog Timer
The AT8xC51SND2C implement a hardware Watchdog Timer (WDT) that automatically resets
the chip if it is allowed to time out. The WDT provides a means of recovering from routines that
do not complete successfully due to software or hardware malfunctions.
12.1 Description
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in
Figure 12-1, the 14-bit prescaler is fed by the WDT clock detailed in Section “Watchdog Clock
Controller”, page 60.
The Watchdog Timer Reset register (WDTRST, see Table 12-2) provides control access to the
WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 12-4) provides time-
out period programming.
Three operations control the WDT:
• Chip reset clears and disables the WDT.
• Programming the time-out value to the WDTPRG register.
• Writing a specific 2-Byte sequence to the WDTRST register clears and enables the WDT.
Figure 12-1. WDT Block Diagram
WDT
CLOCK
÷6
14-bit Prescaler
RST
7-bit Counter
OV
RST
SET
To internal reset
System Reset
1Eh-E1h Decoder _EN
RST
MATCH
WDTRST
WTO2:0
WDTPRG.2:0
OSC
CLOCK
Pulse Generator
RST
12.2 Watchdog Clock Controller
As shown in Figure 12-2 the WDT clock (F_WDT) is derived from either the peripheral clock (F_PER)
or the oscillator clock (F_OSC) depending on the WTX2 bit in CKCON register. These clocks are
issued from the Clock Controller block as detailed in Section "Clock Controller", page 13. When
WTX2 bit is set, the WDT clock frequency is fixed and equal to the oscillator clock frequency
divided by 2. When cleared, the WDT clock frequency is equal to the oscillator clock frequency
divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.
Figure 12-2. WDT Clock Controller and Symbol
PER
CLOCK
0
1
OSC
CLOCK
÷2
WTX2
CKCON.6
WDT Clock
WDT
CLOCK
WDT Clock Symbol
60 AT8xC51SND2C/MP3B
4341H–MP3–10/07