AT83SND2C_14 Datasheet, PDF (182/242 Pages) ATMEL Corporation – MPEG I/II-Layer 3 Hardwired Decoder

Figure 21-2. Complete Data Transfer on TWI Bus
21.1.1
SDA
MSB
SCL
S
Slave Address
1
2
R/W ACK
direction signal
bit from
receiver
8
9
Nth data Byte
ACK
signal
from
receiver
1
2
8
9
P/S
Clock Line Held Low While Serial Interrupts Are Serviced
The four operating modes are:
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver
Data transfer in each mode of operation are shown in Figure 21-3 through Figure 21-6. These
figures contain the following abbreviations:
A
Acknowledge bit (low level at SDA)
A
Not acknowledge bit (high level on SDA)
Data 8-bit data Byte
S
START condition
P
STOP condition
MR
Master Receive
MT
Master Transmit
SLA
Slave Address
GCA General Call Address (00h)
R
Read bit (high level at SDA)
W
Write bit (low level at SDA)
In Figure 21-3 through Figure 21-6, circles are used to indicate when the serial interrupt flag is
set. The numbers in the circles show the status code held in SSSTA. At these points, a service
routine must be executed to continue or complete the serial transfer. These service routines are
not critical since the serial transfer is suspended until the serial interrupt flag is cleared by
software.
When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the
appropriate service routine. For each status code, the required software action and details of the
following serial transfer are given in Table 21-2 through Table 21-6.
Bit Rate
The bit rate can be selected from seven predefined bit rates or from a programmable bit rate
generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 21-9). The
predefined bit rates are derived from the peripheral clock (F_PER) issued from the Clock Controller
block as detailed in section "Oscillator", page 13, while bit rate generator is based on timer 1
overflow output.
182 AT8xC51SND2C/MP3B
4341H–MP3–10/07