AT83SND2C_14 Datasheet, PDF (149/242 Pages) ATMEL Corporation – MPEG I/II-Layer 3 Hardwired Decoder

AT8xC51SND2C/MP3B
The interrupt request is generated each time an unmasked flag is set, and the global MMC con-
troller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This
implies that register content must be saved and tested interrupt flag by interrupt flag to be sure
not to forget any interrupts.
Figure 18-20. MMC Controller Interrupt System
MCBI
MMINT.7
EORI
MMINT.6
EOCI
MMINT.5
EOFI
MMINT.4
F2FI
MMINT.3
F1FI
MMINT.2
F2EI
MMINT.1
F1EI
MMINT.0
MCBM
MMMSK.7
EORM
MMMSK.6
EOCM
MMMSK.5
EOFM
MMMSK.4
F2FM
MMMSK.3
F1FM
MMMSK.2
F2EM
MMMSK.1
F1EM
MMMSK.0
EMMC
IEN1.0
MMC Interface
Interrupt Request
4341H–MP3–10/07
149