AT83SND2C_14 Datasheet, PDF (28/242 Pages) ATMEL Corporation – MPEG I/II-Layer 3 Hardwired Decoder

DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses
83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 6-
2) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 7-6).
Figure 7-6. Dual Data Pointer Implementation
DPTR0
DPTR1
DPL0
DPL1
DPH0
DPH1
0
DPL
1
DPS AUXR1.0
0
DPH
1
DPTR
7.3.2
Application
Software can take advantage of the additional data pointers to both increase speed and reduce
code size, for example, block operations (copy, compare, search …) are well served by using
one data pointer as a “source” pointer and the other one as a “destination” pointer.
Below is an example of block move implementation using the 2 pointers and coded in assem-
bler. The latest C compiler also takes advantage of this feature by providing enhanced algorithm
libraries.
The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in
the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to
a particular state, but simply toggles it. In simple routines, such as the block move example, only
the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words,
the block move routine works the same whether DPS is '0' or '1' on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added
AUXR1
EQU 0A2h
move:
mov
inc
mov
mv_loop: inc
movx
inc
inc
movx
inc
jnz
end_move:
DPTR,#SOURCE ; address of SOURCE
AUXR1
; switch data pointers
DPTR,#DEST ; address of DEST
AUXR1
; switch data pointers
A,@DPTR
; get a Byte from SOURCE
DPTR
; increment SOURCE address
AUXR1
; switch data pointers
@DPTR,A
; write the Byte to DEST
DPTR
; increment DEST address
mv_loop
; check for NULL terminator
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