AT17F080_14 Datasheet, PDF(6/19 Page) ATMEL Corporation – In-System Programmable (ISP) via 2-wire Bus

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AT17F080_14 Datasheet, PDF (6/19 Pages) ATMEL Corporation – In-System Programmable (ISP) via 2-wire Bus

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5.4 PAGESEL[1:0](2)

Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial

configuration download. The address space for each of the pages is shown in Table 5-2. When

SER_EN is Low (ISP mode) these pins have no effect.

Table 5-2. Address Space

Paging Decodes

PAGESEL = 00, PAGE_EN = 1

PAGESEL = 01, PAGE_EN = 1

PAGESEL = 10, PAGE_EN = 1

PAGESEL = 11, PAGE_EN = 1

PAGESEL = XX, PAGE_EN = 0

AT17F040 (4 Mbits)

00000 â 0FFFFh

10000 â 1FFFFh

20000 â 2FFFFh

30000 â 3FFFFh

00000 â 3FFFFh

AT17F080 (8 Mbits)

00000 â 1FFFFh

20000 â 3FFFFh

40000 â 5FFFFh

60000 â 7FFFFh

00000 â 7FFFFh

5.5 RESET/OE(1)

Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on

RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the

data output driver.

5.6 CE(1)

Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address

counter and enables the data output driver. A High level on CE disables both the address and bit

counters and forces the device into a low-power standby mode. Note that this pin will not

enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).

5.7 GND

5.8 CEO

Ground pin. A 0.2 ÂµF decoupling capacitor between VCC and GND is recommended.

Chip Enable Output (when SER_EN is High). This output goes Low when the internal address

counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value

is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the

4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the

address maximum value is the highest address in the device, see Table 5-2 on page 6. In a

daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE

input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will

then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is

read again.

Notes: 1. This pin has an internal 20 kâ¦ pull-up resistor.

2. This pin has an internal 30 kâ¦ pull-down resistor.

6 AT17F040/080

3039KâCNFGâ2/08

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