AT17F080_14 Datasheet, PDF (5/19 Pages) ATMEL Corporation – In-System Programmable (ISP) via 2-wire Bus

AT17F040/080
5. Pin Description
Table 5-1. Pin Description
Name
DATA
CLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/OE
CE
GND
CEO
A2
READY
SER_EN
V_CC
8
I/O
LAP
I/O
1
I
2
I
–
I
–
I
–
I
3
I
4
–
5
O
6
I
O
–
I
7
–
8
AT17F040
20
PLCC
2
4
16
11
7
6
8
10
14
15
17
20
20 PLCC
(Virtex)
1
3
–
–
–
8
10
11
13
15
18
20
8
LAP
1
2
–
–
–
3
4
5
6
–
7
8
AT17F080
20
PLCC
2
4
16
11
7
6
8
10
14
15
17
20
44
TQFP
40
43
39
14
19
13
15
18
21
23
35
38
5.1 DATA⁽¹⁾
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2 CLK⁽¹⁾
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5.3 PAGE_EN⁽²⁾
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes: 1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
5
3039K–CNFG–2/08