AT91RM9200_06 Datasheet, PDF (577/689 Pages) ATMEL Corporation – ARM920T-based Microcontroller

AT91RM9200
• EP2INT: Endpoint 2 Interrupt Status
0 = No Endpoint2 Interrupt pending.
1 = Endpoint2 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading UDP_CSR2:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding UDP_CSR2 bit.
• EP3INT: Endpoint 3 Interrupt Status
0 = No Endpoint3 Interrupt pending.
1 = Endpoint3 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading UDP_CSR3:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding UDP_CSR3 bit.
• EP4INT: Endpoint 4 Interrupt Status
0 = No Endpoint4 Interrupt pending.
1 = Endpoint4 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading UDP_CSR4:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding UDP_CSR4 bit.
• EP5INT: Endpoint 5 Interrupt Status
0 = No Endpoint5 Interrupt pending.
1 = Endpoint5 Interrupt has been raised.
1768G–ATARM–29-Sep-06
577