AT91RM9200_06 Datasheet, PDF (285/689 Pages) ATMEL Corporation – ARM920T-based Microcontroller

AT91RM9200
23.6.9 PMC Clock Generator PLL A Register
Register Name:
CKGR_PLLAR
Access Type:
Read/Write
31
30
29
28
27
26
25
24
–
–
1
–
–
MULA
23
22
21
20
19
18
17
16
MULA
15
14
13
12
11
10
9
8
OUTA
PLLACOUNT
7
6
5
4
3
2
1
0
DIVA
Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the Clock Generator.
Value to be written in CKGR_PLLAR must not be the same as current value in CKGR_PLLAR.
• DIVA: Divider A
DIVA
0
1
2 - 255
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the Main Clock divided by DIVA.
• PLLACOUNT: PLL A Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLL A Clock Frequency Range
OUTA
0
0
0
1
1
0
1
1
PLL A Frequency Output Range
80 MHz to 160 MHz
Reserved
150 MHz to 240 MHz
Reserved
• MULA: PLL A Multiplier
0 = The PLL A is deactivated.
1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1.
1768G–ATARM–29-Sep-06
285