AT91RM9200_06 Datasheet, PDF (221/689 Pages) ATMEL Corporation – ARM920T-based Microcontroller

AT91RM9200
Figure 20-5. Asynchronous Read and Write Accesses with Non-multiplexed Address and Data
BFCS
BFCK
A[24:0]
Read Address
Write Address
BFAVD
AVL
BFOE
AVL
BFWE
D[15:0]
Output
D[15:0]
Input
Data
Data
OEL = 1
Asynchronous
Read Access
Asynchronous
Write Access
Address Valid Latency = 4 BFCK cycles (AVL field = 3)
Output Enable Latency (OEL) = 1 BFCK cycle
20.6.4
Burst Flash Controller Synchronous Mode
Writing the Burst Flash Controller Operating Mode field (BFCOM) to 2 (See “Burst Flash Control-
ler Mode Register” on page 227) puts the BFC in Burst Mode. The BFC Clock is driven on the
BFCK pin. Only read accesses are treated and write accesses are ignored. The BFC supports
read access of bytes, half-words or words.
20.6.4.1
Burst Read Protocols
The BFC supports two burst read protocols:
• Clock Controlled Address Advance, the internal address of the burst Flash is automatically
incremented at each BFCK cycle.
• Signal Controlled Address Advance, the internal address of the burst Flash is incremented
only when the BFBAA signal is active.
20.6.4.2
Read Access in Burst Mode
When a read access is requested in Burst Mode, the requested address is registered in the
BFC. For subsequent read accesses, the address is compared to the previous one. Then the
two following cases are considered:
1. In case of a non-sequential access, the current burst is broken and the BFC launches a
new burst by performing an address latch cycle. The address is presented on the
address bus in any case and on the data bus if the multiplexed bus option is enabled.
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