AT90USB647_14 Datasheet, PDF (57/456 Pages) ATMEL Corporation – 135 powerful instructions – most single clock cycle execution

AT90USB64/128
9. System control and reset
9.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. This is also the case if the Reset Vector is in the Application section while the Interrupt
Vectors are in the Boot section or vice versa. The circuit diagram in Figure 9-1 on page 58
shows the reset logic. Table 9-1 on page 58 defines the electrical parameters of the reset
circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in “Clock sources” on page 41.
9.2 Reset sources
The Atmel AT90USB64/128 has five sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (V_POT)
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the minimum pulse length
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog is enabled
• Brown-out Reset. The MCU is reset when the supply voltage V_CC is below the Brown-out
Reset threshold (V_BOT) and the Brown-out Detector is enabled
• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one
of the scan chains of the JTAG system. Refer to Section “IEEE 1149.1 (JTAG) boundary-
scan” on page 333 for details
57
7593L–AVR–09/12