AT90USB647_14 Datasheet, PDF (208/456 Pages) ATMEL Corporation – 135 powerful instructions – most single clock cycle execution

20.6.3 UCSRnB – USART MSPIM Control and Status Register n B
Bit
Read/write
Initial value
7
6
5
4
3
2
1
0
RXCIEn TXCIEn UDRIE RXENn TXENn -
-
-
UCSRnB
R/W
R/W
R/W
R/W
R/W
R
R
R
0
0
0
0
0
1
1
0
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
• Bit 6 - TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
• Bit 4 - RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override
normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer. Only enabling the receiver in MSPI mode (that is, setting RXENn=1 and
TXENn=0) has no meaning since it is the transmitter that controls the transfer clock and since
only master mode is supported.
• Bit 3 - TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, that is,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnB is written.
20.6.4 UCSRnC – USART MSPIM Control and Status Register n C
Bit
7
6
5
4
3
2
1
0
UMSELn1 UMSELn0 -
-
-
UDORDn UCPHAn UCPOLn UCSRnC
Read/write
R/W
R/W
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
0
1
1
0
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 20-3 on page 209. See
“UCSRnC – USART Control and Status Register n C” on page 196 for full description of the nor-
208 AT90USB64/128
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