AT90USB647_14 Datasheet, PDF (372/456 Pages) ATMEL Corporation – 135 powerful instructions – most single clock cycle execution

30.6.15 Parallel programming characteristics
Figure 30-7. Parallel programming timing, including some general timing requirements.
XTAL1
Data & control
(DATA, XA0/1, BS1, BS2)
PAGEL
WR
t_DVXH
t_XHXL
t_XLWL
t_XLDX
t_BVPH
t_PHPL
t_PLBX t _BVWL
t_PLWL
t_WLWH
WLRL
t_WLBX
RDY/BSY
t_WLRH
Figure 30-8. Parallel programming timing, loading sequence with timing requirements ⁽¹⁾.
XTAL1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
t _XLXH
LOAD DATA LOAD DATA
(HIGH BYTE)
t_XLPH
t_PLXH
LOAD ADDRESS
(LOW BYTE)
BS1
PAGEL
DATA
ADDR0 (Low byte)
DATA (Low byte)
DATA (High byte)
ADDR1 (Low byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 30-7 (that is, t_DVXH, t_XHXL, and t_XLDX) also apply to
loading operation.
Figure 30-9. Parallel programming timing, reading sequence (within the same page) with tim-
ing requirements ⁽¹⁾.
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
t_XLOL
t_BVDV
BS1
OE
t_OLDV
t_OHDZ
DATA
ADDR0 (Low byte)
DATA (Low byte)
DATA (High byte)
ADDR1 (Low byte)
XA0
XA1
372 AT90USB64/128
7593L–AVR–09/12