AT91SAM9261S_1 Datasheet, PDF (526/709 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM9261S
The following flowchart shows how to manage a multiple write block transfer with the PDC (see
Figure 35-10) . Polling or interrupt method can be used to wait for the end of write according to
the contents of the Interrupt Mask Register (MCI_IMR).
Figure 35-10. Multiple Write Functional Flow Diagram
SecnodmmSEaLnEd(C1T) /DtoEsSeEleLcEt CthTe_cCaArdRD
Send SET_BLOCKLEN command(1)
Set the PDCMODE bit
MCI_MR |= PDCMODE
Set the block length
MCI_MR |= (BlockLength << 16)
Configure the PDC channel
MCI_TPR = Data Buffer Address to write
MCI_TCR = BlockLength/4
Send WRITE_MULTIPLE_BLOCK
command(1)
MCI_PTCR = TXTEN
Read status register MCI_SR
Poll the bit
Yes
BLKE = 0?
No
Send STOcoPm_mTRanAdN(S1)MISSION
Poll the bit
Yes
NOTBUSY = 0?
No
RETURN
Note: It is assumed that this command has been correctly sent (see Figure 35-7).
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