ATTINY261_14 Datasheet, PDF (45/206 Pages) ATMEL Corporation – High Performance, Low Power AVR

Table 9-3.
WDE
0
0
1
1
Watchdog Timer Configuration
WDIE
Watchdog Timer State
0
Stopped
1
Running
0
Running
1
Running
Action on Time-out
None
Interrupt
Reset
Interrupt
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the watchdog will not be disabled. Once written to
one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a watchdog disable
procedure. This bit must also be set when changing the prescaler bits. See Section 9.9 “Timed Sequences for Changing the
Configuration of the Watchdog Timer” on page 43
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the watchdog timer is enabled, and if the WDE is written to logic zero, the watchdog
timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled watchdog
timer, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is
set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the watchdog.
In safety level 2, it is not possible to disable the watchdog timer, even with the algorithm described above. See Section 9.9
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43
In safety level 1, WDE is overridden by WDRF in MCUSR. See Section 9.10.1 “MCUSR – MCU Status Register” on page 44
for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared
before disabling the watchdog with the procedure described above. This feature ensures multiple resets during conditions
causing failure, and a safe start-up after the failure.
Note:
If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable
procedure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway
pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To
avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the
initialization routine.
• Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0
The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. The different prescaling
values and their corresponding time-out periods are shown in Table 9-4 on page 45.
Table 9-4. Watchdog Timer Prescale Select
WDP3
0
WDP2
0
WDP1
0
WDP0
0
Number of WDT Oscillator Cycles
2K (2048) cycles
Typical Time-out at
V_CC = 5.0V
16ms
0
0
0
1
4K (4096) cycles
32ms
0
0
1
0
8K (8192) cycles
64ms
0
0
1
1
16K (16384) cycles
0.125s
0
1
0
0
32K (32764) cycles
0.25s
0
1
0
1
64K (65536) cycles
0.5s
0
1
1
0
128K (131072) cycles
1.0s
0
1
1
1
256K (262144) cycles
2.0s
1
0
0
0
512K (524288) cycles
4.0s
1
0
0
1
1024K (1048576) cycles
8.0s
Note: 1. f selecting a reserved code WDT time-out is selected to be one of the legal selections.
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