ATTINY261_14 Datasheet, PDF (167/206 Pages) ATMEL Corporation – High Performance, Low Power AVR

22.9
Serial Downloading
Both the flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND.
The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the programming enable
instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 22-13 on page 167,
the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
Figure 22-7. Serial Programming and Verify⁽¹⁾
+1.8 to 5.5V
MOSI
MISO
SCK
VCC
RESET/ PB7
GND
Note: 1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the CLKI pin.
Table 22-13. Pin Mapping Serial Programming
Symbol
Pins
I/O
MOSI
PB0
I
MISO
PB1
O
SCK
PB2
I
Description
Serial data in
Serial data out
Serial clock
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode
ONLY) and there is no need to first execute the chip erase instruction. The chip erase operation turns the content of every
memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK)
input are defined as follows:
Low: > 2 CPU clock cycles for f_ck < 12MHz, 3 CPU clock cycles for f_ck ≥ 12MHz
High: > 2 CPU clock cycles for f_ck < 12MHz, 3 CPU clock cycles for f_ck ≥ 12MHz
ATtiny261/ATtiny461/ATtiny861/ATtiny461 [DATASHEET] 167
7753G–AVR–06/14