AT32AP7002_09 Datasheet, PDF (44/52 Pages) ATMEL Corporation – AVR 32 32-bit Microcontroller

32054FS–AVR32–09/09
AT32AP7002
Fix/Workaround
Before executing any code the user should enable the RTC with the smallest prescaler and
poll that the RTC is counting before doing anything in your program. Another way to ensure
that the osc32 is valid is to use interrupts with TOP=1.
Example:
//reset the counter register
AVR32_RTC.val = 0x0;
//enable the RTC with the smallest prescaler
AVR32_RTC.ctrl = 0x1;
//wait until the value increases
while(AVR32_RTC.val == 0);
26. SPI can generate a false RXREADY signal in SLAVE mode
In slave mode the SPI can generate a false rxready signal during enabling of the SPI or dur-
ing the first transfer.
Fix/Workaround
1. Set slave mode, set required CPOL/CPHA
2. Enable SPI
3. Set the polarity CPOL of the line in the opposite value of the required one
4. Set the polarity CPOL to the required one.
5. Read the RXHOLDING register
Transfers can now begin and RXREADY will now behave as expected.
27. EBI address lines 23, 24, and 25 are pulled up when booting up
After reset the EBI address lines 23, 24 and 25 are tristated with pullups. Booting from a
flash larger than 8 MB using these lines will fail, as the flash will be accessed with these
address bits set.
Fix/Workaround
Add external pulldown resistors (5 kΩ) on these lines if booting from a flash larger than 8 MB
using these address lines.
28. SSC - Additional delay on TD output
A delay from 2 to 3 system clock cycles is added to TD output when:
TCMR.START = Receive Start,
TCMR.STTDLY = more than ZERO,
RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge
RFMR.FSOS = None (input)
Fix/Workaround
None.
29. SSC - TF output is not correct
TF output is not correct (at least emitted one serial clock cycle later than expected) when:
TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer
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