AT32AP7002_09 Datasheet, PDF (41/52 Pages) ATMEL Corporation – AVR 32 32-bit Microcontroller

32054FS–AVR32–09/09
AT32AP7002
Fix/Workaround
Use slot A.
7. PSIF TXEN/RXEN may disable the transmitter/receiver
Writing a '0' to RXEN will disable the receiver. Writing '0' to TXEN will disable the transmitter.
Fix/Workaround
When accessing the PS/2 Control Register always write '1' to RXEN to keep the receiver
enabled, and write '1' to TXEN to keep the transmitter enabled.
8. PSIF TXRDY interrupt corrupts transfers
When writing to the Transmit Holding Register (THR), the data will be transferred to the data
shift register immediately, regardless of the state of the data shift register. If a transfer is
ongoing, it will be interrupted and a new transfer will be started with the new data written to
THR.
Fix/Workaround
Use the TXEMPTY-interrupt instead of the TXRDY-interrupt to update the THR. This
ensures that a transfer is completed.
9. LCD memory error interupt does not work
Writing to the MERIT-bit in the LCD Interrupt Test Register (ITR) does not cause an interrupt
as intended. The MERIC-bit in the LCD Interrupt Clear Register (ICR) cannot be written.
This means that if the MERIS-bit in ISR is set, it cannot be cleared.
Fix/Workaround
Memory error interrupt should not be used.
10. PWM counter restarts at 0x0001
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
11. PWM channel interrupt enabling triggers an interrupt
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
12. PWM update period to a 0 value does not work
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
13. PWM channel status may be wrong if disabled before a period has elapsed
41