SAM3U Datasheet, PDF (41/59 Pages) ATMEL Corporation – AT91SAM ARM-based Flash MCU

SAM3U Series
10.13 Chip Identification
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
Table 10-1. SAM3U Chip IDs Register - Engineering Samples
Chip Name
Flash Size
KByte
Pin Count
CHIPID_CIDR
SAM3U4C
256
100
0x28000960
SAM3U2C
128
100
0x280A0760
SAM3U1C
64
100
0x28090560
SAM3U4E
256
144
0x28100960
SAM3U2E
128
144
0x281A0760
SAM3U1E
64
144
0x28190560
• JTAG ID: 0x0582A03F
CHIPID_EXID
0x0
0x0
0x0
0x0
0x0
0x0
Table 10-2. SAM3U Chip IDs Register - Revision A Parts
Chip Name
Flash Size
KByte
Pin Count
CHIPID_CIDR
SAM3U4C (Rev A)
256
100
0x28000961
SAM3U2C (Rev A)
128
100
0x280A0761
SAM3U1C (Rev A)
64
100
0x28090561
SAM3U4E (Rev A)
256
144
0x28100961
SAM3U2E (Rev A)
128
144
0x281A0761
SAM3U1E (Rev A)
64
144
0x28190561
• JTAG ID: 0x0582A03F
CHIPID_EXID
0x0
0x0
0x0
0x0
0x0
0x0
10.14 PIO Controllers
• 3 PIO Controllers, PIOA, PIOB, and PIOC, controlling a maximum of 96 I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change, rising edge, falling edge, low level and level interrupt
– Debouncing and Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
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6430ES–ATARM–22-Aug-11