SAM3U Datasheet, PDF (26/59 Pages) ATMEL Corporation – AT91SAM ARM-based Flash MCU

Even in all low power modes, asserting the pin will automatically start-up the chip and erase the
Flash.
7. Processor and Architecture
7.1 ARM Cortex-M3 Processor
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
• Three-stage pipeline.
• Single cycle 32-bit multiply.
• Hardware divide.
• Thumb and Debug states.
• Handler and Thread modes.
• Low latency ISR entry and exit.
7.2 APB/AHB Bridges
The SAM3U product embeds two separated APB/AHB bridges:
• low speed bridge
• high speed bridge
This architecture enables to make concurrent accesses on both bridges.
All the peripherals are on the low-speed bridge except SPI, SSC and HSMCI.
The UART, 10-bit ADC (ADC), 12-bit ADC (ADC12B), TWI0-1, USART0-3, PWM have dedicated
channels for the Peripheral DMA Channels (PDC). These peripherals can not use the DMA
Controller.
The high speed bridge regroups the SSC, SPI and HSMCI. These three peripherals do not have
PDC channels but can use the DMA with the internal FIFO for Channel buffering.
Note that the peripherals of the two bridges are clocked by the same source: MCK.
7.3 Matrix Masters
The Bus Matrix of the SAM3U device manages 5 masters, which means that each master can
perform an access concurrently with others to an available slave.
Each master has its own decoder and specifically defined bus. In order to simplify the address-
ing, all the masters have the same decoding.
Table 7-1.
Master 0
Master 1
Master 2
Master 3
Master 4
List of Bus Matrix Masters
Cortex-M3 Instruction/Data
Cortex-M3 System
Peripheral DMA Controller (PDC)
USB Device High Speed DMA
DMA Controller
26 SAM3U Series
6430ES–ATARM–22-Aug-11